A computer is known to include a central processing unit, system memory, video graphics circuitry, audio processing circuitry, and peripheral ports. The peripheral ports allow the computer to interface with peripheral devices such as printers, monitors, external tape drives, Internet, etc. In such a computer, the central processing unit functions as a host processor while the video graphics circuit functions as a loosely coupled co-processor. In general, the host processor executes applications and, during execution, calls upon the co-processor to execute its particular function. For example, if the host central processing unit requires a drawing operation to be done, it requests, via a command through a command delivery system, the video graphics co-processor to perform the drawing function.
In many situations, the host central processing unit needs to know the current status of the co-processor, or co-processors, before it can continue with processing the particular application and/or before sending new commands to the co-processor. The host central processing unit obtains such status information from the co-processors via a handshaking protocol. In essence, the hosts central processing initiates the handshaking protocol by poling a co-processor to obtain its status and by poling a co-processor register to obtain the stored status. The host processor then determines whether the co-processors status has changed. If so, host processor updates the co-processor register and continues with additional processing operations. If not, the host processor waits unit the co-processor has completed the current task. Such a technique is known as pole and register writes.
To reduce the host processor's idle time while it is waiting for the co-processor, a command first-in, first-out ("FIFO") queue may be incorporated. The command FIFO stores queued commands from the host processor that are awaiting execution by the co-processor. When the co-processor is able to perform a command, it retrieves the command from the command FIFO. As the co-processor executes a queued command, it updates a co-processor register. In this implementation, the host processor needs to verify that the command FIFO is not full and still needs to read the co-processor register to determine the current status of the co-processor. If the command FIFO is relatively small, i.e., holds a limited number of commands, the host processor still experiences wait cycles while the co-processor completes the processing of a command thereby freeing space in the command FIFO.
Increasing the size of the command FIFO, such that the host processor can download as many commands as needed, may reduce the wait cycles. But, by increasing the command FIFO, the required memory is increased, as is the die area, and the cost of the co-processor.
Therefore, a need exists for a method and apparatus that improves concurrency between a host processor and co-processors that substantially eliminates the need for polling and without substantial increase to the size the command FIFO.